1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming semiconductor devices by forming semiconductor channel region materials prior to forming isolation structures, such as trench isolation structures.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (NFET and PFET transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
To make an integrated circuit on a semiconducting substrate, the various semiconductor devices, e.g., transistors, capacitors, etc., are electrically isolated from one another by so-called isolation structures. Currently, most sophisticated integrated circuit devices employ so-called shallow trench isolation (STI) structures. As the name implies, STI structures are made by forming a relatively shallow trench in the substrate and thereafter filling the trench with an insulating material, such as silicon dioxide. Such STI structures are typically the very first structures that are formed when manufacturing semiconductor devices.
One technique used to form STI structures initially involves growing a thin pad oxide layer on the substrate and depositing a pad nitride layer on the pad oxide layer. Thereafter, using traditional photolithography and etching processes, the pad oxide layer and the pad nitride layer are patterned. Then, an etching process is performed to form a trench in the substrate for the STI structure using the patterned pad oxide layer and pad nitride layer as an etch mask. Thereafter, a deposition process, such as the well-known High Aspect Ratio Process (HARP) offered by Applied Materials, is performed to overfill the trenches with an insulating material such as silicon dioxide. The deposited silicon dioxide material is then typically densified by subjecting it to an anneal process in a furnace, e.g., about 1000° C. for a duration of about 30 minutes. The purpose of the densification process is to increase the etch resistance of the silicon dioxide material to later wet etching processes. Thereafter, a chemical mechanical polishing (CMP) process is performed using the pad nitride layer as a polish stop layer to remove the excess insulation material positioned outside of the trenches. Then, a subsequent deglazing (etching) process may be performed to insure that the silicon dioxide insulating material is removed from the surface of the pad nitride layer. This deglaze process may remove some of the material of the STI structures. Thereafter, a wet nitride strip process, e.g., a hot phosphoric acid process, is performed to selectively remove the pad nitride layer relative to the pad oxide layer and the STI structure. If desired, the pad oxide layer may also be removed at this time by performing a quick wet etching process using a dilute HF chemistry. Alternatively, the pad oxide layer may be left in place or removed at a later point in the process flow.
Numerous processing operations are performed in a very detailed sequence, or process flow, to form integrated circuit devices, e.g., deposition processes, etching processes, heating processes, masking operations, etc. One problem that arises with current processing techniques is that, after the STI regions are formed, at least portions of the STI regions are exposed to many subsequent etching or cleaning processes that tend to consume, at least to some degree, portions of the STI structures subjected to such etching processes. The attacks are not uniform across the surface of the STI structure due to, for example, masking only certain portions of the STI structure during some etching processes. As a result, there is an uneven loss of material in the STI structure, sometimes referred to as “divots.” Uneven STI structures can be problematic for several reasons. For example, the uneven topography of such STI structures can make it more difficult for lithographic processes to achieve sufficient focus and pattern resolution. Additionally, if the depth of the divots is too great, the chances that there may be a loss of gate encapsulation as processing continue may occur. The presence of such divots may also cause an increase in the degree of undesirable “footing” of the gate materials when they are patterned to define the gate structure. In some cases, the depth of the divots may be so great that there is a risk of incomplete etching of one or more of the conductive materials in the gate structure such that there is a short circuit created between adjacent gate structures. Such a situation is sometimes referred to as the creation of undesirable “poly stringers” between adjacent gate structures. As a result, the STI structures may not perform their isolation function as intended, which may result in problems such as increased leakage currents, device failure, etc.
One illustrative situation where divots may be created in STI structures involves the formation of NFET and PFET transistor devices on the same substrate, i.e., CMOS (complementary metal oxide semiconductor) technology, due to different materials and construction techniques used in forming the two different types of devices. Typically, manufacturing integrated circuit devices using CMOS technology involves many masking operations wherein one of the device regions is masked, e.g., the N-active region, while the other region, e.g., the P-active region, is subjected to various processing operations, e.g., etching, selective deposition of materials, etc. Since the various mask layers used in manufacturing CMOS-based products typically only cover about half of the STI structures, the STI structures are subjected to different processing operations. As a result, undesirable divots are formed in STI structures in CMOS-based products.
FIG. 1 depicts an illustrative prior art CMOS-based device 100 that is generally comprised of a partially formed NFET transistor 100N and a partially formed PFET transistor 100P formed in and above a semiconducting substrate 10 comprised of silicon. The illustrative transistors 100N, 100P are separated by an STI structure 12 formed in the substrate 10, which was the first structure formed on the substrate 10. The substrate 10 may have a variety of configurations, such as the depicted silicon-on-insulator (SOI) structure having a bulk silicon layer 10A, a buried insulation layer 10B and an active layer 10C. The substrate 10 may also have a simple bulk silicon configuration. The STI structure 12 exhibits an uneven surface due to the presence of illustrative and simplistically depicted divots 12A that occur as a result of the many masking and etching processes performed on different regions of the device 100.
At the stage of manufacture depicted in FIG. 1, the transistors 100N, 100P are each comprised of a gate structure 20 and source/drain regions 30. The gate structure 20 may include a gate insulation layer 22, a high-k insulation layer 24, a gate electrode 26 and sidewall spacers 28. The gate electrode 26 may be made of one or more layers of a variety of conductive materials, such as lanthanum (for the NFET transistor 100N) and aluminum (for the PFET transistor 100P). In some cases, the PFET transistor 100P may have an additional work function layer 25, such as titanium nitride, that may not be present in the NFET transistor 100N. Typically, during the formation of the PFET transistor 100P, a layer of channel semiconductor material 32, e.g., silicon/germanium, is selectively formed on the active layer 10C in the P-active region where the PFET transistor 100P will be formed to enhance the performance of the PFET transistor 100P. Typically, such a layer of channel semiconductor material 32 is not formed for the NFET transistor 100N.
Prior to selectively forming the layer of channel semiconductor material 32 for the PFET transistor 100P only, the N-active region (where the NFET transistor 100N will be formed) and part of the STI structure 12 are masked, while the P-active region and the unmasked portion of the STI structure 12 will be exposed for further processing. In some cases, an etching process is performed to slightly recess the P-active region such that, after the channel semiconductor material 32 is formed, the upper surface of the channel semiconductor material 32 will be approximately level with the upper surface of the substrate in the N-active region. As mentioned above, the unmasked portion of the STI structure 12 will be exposed to this etching process and some of the material of the STI structure 12 will be consumed during this etching process, thereby creating an uneven upper surface on the STI structure 12.
The present disclosure is directed to various methods of forming semiconductor devices that may eliminate or at least reduce one or more of the problems identified above.